000			00680nam a22001457a 4500
008			210319b ||||| |||| 00| 0 eng d
020			_a81-7319-100-X
082			_223 _a004.22 _bFLY
100			_aFlynn Michael J.
245			_aComputer Architecture _bPipelined and Parallel Processor Design _cMichael J.Flynn _hEnglish
260			_aNew Delhi _bNarosa Publishing House _c1998
300			_axv-788 p. _bSoft Bound _c13.6*21 cm
505			_a1. Architecture and Machine 2. Time,area and Instruction sets 3. Data: How Programs Behave 4. Pipelined Processor Design 5. Cache memory 6. Memory system Design 7. Concurrent Procedure 8. Shared Memory Multiprocessors
942			_2ddc _cBK
999			_c6637 _d6637